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IEEE Test Interface (STIL) and Memory Core Test Language - IEEE 1450(TM) Series (Bundle)

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The 1450 test interface (STIL) and Core Test language bundle provides an interface between digital test generation tools and test equipment and interface between digital test generation tools and test equipment. It defines structures in STIL for specifying the DC conditions for a device under test. The STIL environment supports transferring tester-independent test programs to a specific ATE system. The Core Test Language (CTL) is a language created for a System-on-Chip flow (or SoC flow), where a design created by one group is reused as a sub-design of a design created by another group. It defines how the necessary information is passed from scan insertion to pattern generation and from pattern generation to diagnosis such that different tool vendors could be used for each step independent of on-chip scan compression logic used. It defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an System-on-Chip flow (SoC).
Extensions to the test interface language (contained in this bundle) are defined that (1) facilitate the use of the language in the design environment and (2) facilitate the use of the language for large designs encompassing subdesigns with reusable patterns. Examples of the DC conditions for device power supplies are: device power supply setup, power sequencing to the device and power supply limit. Although native STIL data are tester independent, the actual process of mapping the test program onto tester resources may be critical, and it is necessary to be able to completely and unambiguously specify how the STIL programs and patterns are mapped onto the tester resources. TRC (which stands for either tester resource constraints or tester rules checking, depending on the usage) is an extension to the STIL language to facilitate this operation. In an SoC flow, the smaller design embedded in the larger design is commonly called a core and the larger design is commonly called the SoC. The core is a design provided by a core provider, and the task of incorporating the sub-design into the SoC is called Core System Integration. It facilitates the development and reuse of test and repair mechanisms for memories. It defines constructs that represent the test structures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6(TM)-2005. As a result of this extension, CTLs limitations of handling memories are addressed. This bundle contains: IEEE 1450-1999, IEEE 1450.1-2005, IEEE 1450.2-2002, IEEE 1450.3-2007, IEEE 1450.4-2017, IEEE1450.6-2006, IEEE 1450.6.1-2009, IEEE 1450.6.2-2014

Author IEEE
Editor IEEE
Document type Set
Format File
Year 2018
Country USA